UART Baud Rate Error Calculator — register value and % error
Register value and percentage error for any MCU clock and baud rate, with a verdict on whether the link will actually be reliable.
Example: 115.2 kBd from a 16 MHz clock gives UBRR = 8, an actual 111111.1 baud — -3.549% error. Will not work reliably.
Check it against real silicon
Chiprun runs your firmware on an emulated microcontroller and hands back the UART output, so you can confirm these numbers rather than trusting them.
Formula
divisor = f_clk / (oversampling × baud)Worked example
115.2 kBd from a 16 MHz clock gives UBRR = 8, an actual 111111.1 baud — -3.549% error. Will not work reliably.
divisor = f_clk / (oversampling × baud)
divisor = 16 MHz / (16 × 115200)
divisor = 8.6806 → rounds to 9
UBRR = divisor − 1
UBRR = 9 − 1
UBRR = 8
actual = f_clk / (oversampling × divisor)
actual = 16 MHz / (16 × 9)
actual = 111111.11 baud
Rounding the divisor is what creates the error — the clock cannot divide exactly into 115200.
Frequently asked questions
How much baud rate error can a UART tolerate?
Roughly 2% per end for standard 8N1 framing. The receiver samples the middle of each bit and resynchronises only on the start bit, so error accumulates across the ten bit-times of a frame. Both ends contribute, so two devices each 2% off in opposite directions will drop frames.
Why is 115200 baud unreliable on a 16 MHz AVR?
16 MHz does not divide evenly by 16 × 115200. The divisor works out at 8.68, rounds to 9, and yields 111111 baud — a 3.5% error, which is past the practical limit. Setting U2X halves the oversampling and brings it back to about 2%, and an 11.0592 MHz crystal removes the error entirely.
What are 11.0592 MHz and 14.7456 MHz crystals for?
They are exact multiples of standard baud rates. 11.0592 MHz is 115200 × 96, so every common baud rate divides out of it with no remainder and zero error. That is the only reason such odd-looking frequencies exist.
What does U2X or double-speed mode do?
It changes oversampling from 16 samples per bit to 8, which doubles the achievable baud rate for a given clock and often lands closer to the target. The trade-off is less noise immunity, since each bit is judged from half as many samples.
Is a negative error better than a positive one?
Not inherently — what matters is the magnitude, and how it combines with the other end's error. If you know the device you are talking to runs slightly fast, choosing a divisor that errs slow gives you more combined margin.
Related tools
Timer & Prescaler Calculator
Every valid prescaler and reload pair for a target frequency on AVR, STM32, PIC and RP2040 — ranked by error, with C you can paste.
Firmware
Clock Tree & PLL Configurator
Solve PLL M/N/P/Q dividers for a target system clock from your crystal, respecting each stage's legal range.
Firmware
SPI Clock Divider Calculator
Prescaler settings to hit a target SPI clock without exceeding your peripheral's maximum.
Firmware
CAN Bus Bit Timing Calculator
Every valid TSEG1/TSEG2/SJW combination for your clock and bitrate, ranked by sample-point quality, with the register value.
Firmware
CRC Calculator
CRC-8, CRC-16 (CCITT, Modbus, XMODEM) and CRC-32 over hex or ASCII input, with the polynomial and shift steps explained.
Firmware
Hex, Binary & Decimal Converter
Convert between hex, binary, decimal, octal and ASCII, with width-aware bit grids and endianness swapping.
Firmware