SPI Clock Divider Calculator — prescaler and actual clock

Prescaler settings to hit a target SPI clock without exceeding your peripheral's maximum.

Example: A ÷16 prescaler gives 5.25 MHz from a 84 MHz clock — the fastest that stays within the device's 10 MHz limit.

Inputs

Peripheral clock(Hz)

Often APB1 or APB2, not the core clock.

Device maximum clock(Hz)

From the slave's datasheet — the fastest it will accept.

MCU family

Result

Divider

÷16

BR: 3
Actual SPI clock: 5.25 MHz
Of device maximum: 52.5%
Bit period: 190.5 ns
Time per byte: 1.524 µs

Dividers are discrete, so the achievable clock is 5.25 MHz — 52.5% of the device's 10 MHz limit. The next step up would be 10.5 MHz, which exceeds it.
This always rounds the divider up, never to nearest. Unlike a UART baud rate — where a small error either way just costs margin — exceeding a slave's maximum SPI clock makes it return corrupt data or nothing at all.
You are leaving 48% of the device's speed unused. A different peripheral clock could land closer to the limit if throughput matters here.

Available dividers on this family

Divider	BR	SPI clock	Within limit
÷2	0	42 MHz	no
÷4	1	21 MHz	no
÷8	2	10.5 MHz	no
÷16	3	5.25 MHz	yes
÷32	4	2.625 MHz	yes
÷64	5	1.313 MHz	yes
÷128	6	656.3 kHz	yes
÷256	7	328.1 kHz	yes

/* generated by urdb.io/tools/spi-clock-divider */
/* 84 MHz / 16 = 5.25 MHz */
SPI1->CR1 &= ~SPI_CR1_BR;
SPI1->CR1 |= (3 << SPI_CR1_BR_Pos);   /* ÷16 */

Check it against real silicon

Chiprun runs your firmware on an emulated microcontroller and hands back the UART output, so you can confirm these numbers rather than trusting them.

Chiprun docs

Formula

f_SPI = f_peripheral / divider

Worked example

A ÷16 prescaler gives 5.25 MHz from a 84 MHz clock — the fastest that stays within the device's 10 MHz limit.

smallest divider with f_clk / divider ≤ f_max
84 MHz / 16 = 5.25 MHz ≤ 10 MHz
÷16
Rounding up is mandatory — exceeding the slave's maximum is a functional failure, not just an error.

Frequently asked questions

How do I pick an SPI clock divider?

Take the smallest divider whose resulting clock stays at or below the slave's maximum. Because dividers are powers of two on most microcontrollers, you often end up well under the device's limit — that is normal and safe.

Why round up rather than to the nearest divider?

Because the target is a hard maximum, not a nominal value. A UART running 2% fast still works; an SPI slave clocked past its rated maximum returns corrupt data or nothing. Always land at or below the limit.

Which clock feeds the SPI peripheral?

The APB bus clock it sits on, not the core clock. On STM32 parts SPI1 is usually on APB2 and SPI2/3 on APB1, and the two buses often run at different speeds — so the same divider gives different results on different instances.

Why does my SPI device fail at higher clock speeds?

Often signal integrity rather than the divider. The slave's rated maximum assumes a clean edge at its own pin; long traces, missing ground return and capacitive loading all degrade that. Slow the clock to confirm, then fix the layout rather than living with the slower speed.

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