PLL Calculator — STM32 clock tree dividers

Solve PLL M/N/P/Q dividers for a target system clock from your crystal, respecting each stage's legal range.

Example: 168 MHz from a 8 MHz crystal: M=4, N=168, P=2, Q=7 — VCO runs at 336 MHz.

Inputs

HSE / crystal(Hz)

Target SYSCLK(Hz)

USB clock needed

Part maximum SYSCLK(Hz)

168 MHz for STM32F407, 180 MHz for F429, 100 MHz for F411.

Result

SYSCLK

168 MHz

PLL_M: 4
PLL_N: 168
PLL_P: 2
PLL_Q: 7
VCO input: 2 MHz
VCO output: 336 MHz

Exact — 168 MHz is reachable from this crystal.
VCO input is 2 MHz, at ST's recommended 2 MHz for lowest jitter.
Q = 7 gives exactly 48 MHz for USB. USB will not enumerate reliably on an approximate clock — the tolerance is 0.25%.

Alternative configurations

M	N	P	Q	VCO in	VCO out	SYSCLK
4	168	2	7	2 MHz	336 MHz	168 MHz
5	210	2	7	1.6 MHz	336 MHz	168 MHz
6	252	2	7	1.333 MHz	336 MHz	168 MHz
7	294	2	7	1.143 MHz	336 MHz	168 MHz
8	336	2	7	1 MHz	336 MHz	168 MHz
4	144	2	6	2 MHz	288 MHz	144 MHz
5	180	2	6	1.6 MHz	288 MHz	144 MHz
6	216	2	6	1.333 MHz	288 MHz	144 MHz

/* generated by urdb.io/tools/pll-calculator */
/* 8 MHz HSE → 168 MHz SYSCLK */
RCC->PLLCFGR = (4 << RCC_PLLCFGR_PLLM_Pos)
             | (168 << RCC_PLLCFGR_PLLN_Pos)
             | (0 << RCC_PLLCFGR_PLLP_Pos)   /* P = 2 */
             | (7 << RCC_PLLCFGR_PLLQ_Pos)
             | RCC_PLLCFGR_PLLSRC_HSE;

Check it against real silicon

Chiprun runs your firmware on an emulated microcontroller and hands back the UART output, so you can confirm these numbers rather than trusting them.

Chiprun docs

Formula

VCO_in = HSE / M    VCO_out = VCO_in × N    SYSCLK = VCO_out / P

Worked example

168 MHz from a 8 MHz crystal: M=4, N=168, P=2, Q=7 — VCO runs at 336 MHz.

VCO_in = HSE / M
8 MHz / 4
2 MHz
Must land between 1 and 2 MHz. This is the constraint people miss.
VCO_out = VCO_in × N
2 MHz × 168
336 MHz
Must land between 100 and 432 MHz.
SYSCLK = VCO_out / P
336 MHz / 2
168 MHz
USB = VCO_out / Q
336 MHz / 7
48 MHz

Frequently asked questions

How do STM32 PLL dividers work?

Three stages in series. M divides the crystal down to a VCO input between 1 and 2 MHz, N multiplies that up to a VCO output between 100 and 432 MHz, and P divides that down to SYSCLK. Every stage has its own legal range, so a combination giving the right SYSCLK can still be invalid.

Why should the VCO input be 2 MHz?

It minimises PLL jitter. The range allows 1 to 2 MHz, but ST recommends 2 MHz, and jitter matters if you are sampling analogue signals or generating precise timing. With an 8 MHz crystal that means M = 4.

Why is it hard to get both 168 MHz and USB?

USB needs exactly 48 MHz, which requires the VCO output to be an integer multiple of 48 MHz. That constraint plus the SYSCLK requirement plus the VCO range leaves very few valid combinations — it is why 8 MHz crystals and 168 MHz are such a common pairing, since 336 MHz divides by both 2 and 7.

Can I run USB on an approximate 48 MHz?

No. The USB specification allows about 0.25% tolerance, and the peripheral will fail to enumerate outside it. If the PLL cannot produce an exact 48 MHz alongside your SYSCLK, use a separate clock source for USB.

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