CAN Bus Bit Timing Calculator — BRP, TSEG1, TSEG2 and sample point

Every valid TSEG1/TSEG2/SJW combination for your clock and bitrate, ranked by sample-point quality, with the register value.

Example: 500 kbit/s from a 36 MHz clock: BRP 9, TSEG1 6, TSEG2 1 — 8 tq per bit with a 87.5% sample point.

Inputs

CAN clock(Hz)

The peripheral clock feeding the CAN controller, often APB1.

Bit rate(bit/s)

Target sample point

0.875 for most rates; CiA suggests 0.75 above 800 kbit/s.

SJW

How far the controller may shift a bit edge to resynchronise.

Result

BRP (prescaler)

TSEG1: 6 tq
TSEG2: 1 tq
Sample point: 87.5%
Time quanta per bit: 8
Time quantum: 250 ns
Bit time: 2 µs
CAN_BTR: 0x00050008

Exact — 87.5% matches your target precisely, with 8 time quanta per bit.
Only 8 time quanta per bit. BRP 4 with TSEG1 15 / TSEG2 2 gives 18 tq at 88.89% — coarser on sample point but more tolerant of oscillator mismatch between nodes.
Every node on the bus must use the same bit rate AND a compatible sample point. Two controllers at 500 kbit/s with sample points at 75% and 87.5% produce intermittent errors that look exactly like noise or bad termination.
SJW of 1 equals TSEG2. SJW must not exceed TSEG2, and keeping it below leaves room for resynchronisation without shifting the sample point.

Alternative segment layouts

BRP	TSEG1	TSEG2	tq/bit	Sample point
9	6	1	8	87.5%
4	15	2	18	88.89%
8	7	1	9	88.89%
4	14	3	18	83.33%
6	9	2	12	83.33%
6	10	1	12	91.67%
4	16	1	18	94.44%
4	13	4	18	77.78%

/* generated by urdb.io/tools/can-bit-timing */
/* 500 kbit/s from 36 MHz, 87.5% sample point */
CAN1->BTR = (0 << 24)   /* SJW   = 1 tq */
          | (0 << 20)   /* TSEG2 = 1 tq */
          | (5 << 16)   /* TSEG1 = 6 tq */
          | (8);          /* BRP   = 9 */
/* = 0x00050008 */

Check it against real silicon

Chiprun runs your firmware on an emulated microcontroller and hands back the UART output, so you can confirm these numbers rather than trusting them.

Chiprun docs

Formula

bit time = (1 + TSEG1 + TSEG2) × BRP / f_clk    sample = (1 + TSEG1) / total tq

Calculations follow ISO 11898-1.

Worked example

500 kbit/s from a 36 MHz clock: BRP 9, TSEG1 6, TSEG2 1 — 8 tq per bit with a 87.5% sample point.

total tq = f_clk / (BRP × bitrate)
36 MHz / (9 × 500 kbit/s)
8 tq
Must be a whole number, and between 8 and 25, for the controller to resynchronise.
1 (SYNC_SEG) + TSEG1 + TSEG2 = total tq
1 + 6 + 1
8
sample point = (1 + TSEG1) / total tq
(1 + 6) / 8
87.5%
Where in the bit the controller reads the level. Late is better for propagation delay, but leaves less room to resynchronise.

Frequently asked questions

What is the CAN sample point and why does it matter?

The position within each bit where the controller reads the level, expressed as a percentage. Every node must agree closely — two devices at the same bit rate but with sample points at 75% and 87.5% will produce intermittent errors that look like noise or bad termination. CiA recommends 87.5% for most rates.

Why do CAN peripherals need such specific clock frequencies?

Because the clock must divide into the bit rate by a whole number of time quanta, between 8 and 25. Frequencies like 16, 36 and 40 MHz are chosen precisely because they divide cleanly into standard CAN rates. An arbitrary clock often has no valid solution at all.

What is SJW?

Synchronisation jump width — how many time quanta the controller may shift a bit boundary to stay in step with the transmitter. It compensates for oscillator drift between nodes. It must not exceed TSEG2, and 1 tq is adequate for most designs with crystal-accurate clocks.

Should I prefer more time quanta per bit?

Generally yes, when the sample point comes out the same. More time quanta means finer resynchronisation steps and more tolerance of oscillator mismatch. The trade-off is that fewer combinations hit an exact sample point, so this tool ranks accuracy first and shows the alternatives.

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