Register Bitfield Decoder

Paste a register value and a field layout to get a decoded table — with presets for common STM32 and AVR registers.

Example: 0x00010023 decodes to CEN=1, DIR=0, CMS=1, ARPE=0, CKD=0, UIF=1.

Inputs

Field layout

NAME:high:low for a range, NAME:bit for one bit. The default is STM32 TIMx_CR1.

Result

0x00010023

Binary: 0000 0000 0000 0001 0000 0000 0010 0011
Fields decoded: 6
CEN: 1
DIR: 0
CMS: 1 (0x1, 0b01)
ARPE: 0
CKD: 0 (0x0, 0b00)
UIF: 1

Bits set outside every named field: 0x2. Those are usually reserved. Most reference manuals require reserved bits to keep their reset value, so read-modify-write rather than assigning the whole register.
Reading a register does not always return what you wrote. Write-only bits read as zero, clear-on-read flags change state as you look at them, and some fields are only valid while the peripheral is disabled.

Fields

Field	Bits	Width	Value	Hex	Binary
CEN	0	1	1	0x1	1
DIR	4	1	0	0x0	0
CMS	6:5	2	1	0x1	01
ARPE	7	1	0	0x0	0
CKD	9:8	2	0	0x0	00
UIF	16	1	1	0x1	1

/* generated by urdb.io/tools/bitfield-decoder */
#define CEN_Pos   0
#define CEN_Msk   (0x1UL << CEN_Pos)
#define DIR_Pos   4
#define DIR_Msk   (0x1UL << DIR_Pos)
#define CMS_Pos   5
#define CMS_Msk   (0x3UL << CMS_Pos)
#define ARPE_Pos   7
#define ARPE_Msk   (0x1UL << ARPE_Pos)
#define CKD_Pos   8
#define CKD_Msk   (0x3UL << CKD_Pos)
#define UIF_Pos   16
#define UIF_Msk   (0x1UL << UIF_Pos)

uint32_t reg = 0x00010023UL;
uint32_t cen = (reg & CEN_Msk) >> CEN_Pos;   /* 1 */
uint32_t dir = (reg & DIR_Msk) >> DIR_Pos;   /* 0 */
uint32_t cms = (reg & CMS_Msk) >> CMS_Pos;   /* 1 */

Check it against real silicon

Chiprun runs your firmware on an emulated microcontroller and hands back the UART output, so you can confirm these numbers rather than trusting them.

Chiprun docs

Formula

field = (register >> low) & ((1 << (high − low + 1)) − 1)

Worked example

0x00010023 decodes to CEN=1, DIR=0, CMS=1, ARPE=0, CKD=0, UIF=1.

CEN = (reg >> 0) & 0x1
(0x00010023 >> 0) & 0x1
1
DIR = (reg >> 4) & 0x1
(0x00010023 >> 4) & 0x1
0
CMS = (reg >> 5) & 0x3
(0x00010023 >> 5) & 0x3
1
ARPE = (reg >> 7) & 0x1
(0x00010023 >> 7) & 0x1
0

Frequently asked questions

How do I extract a bitfield from a register?

Shift right by the field's low bit, then mask off the width: `(reg >> low) & ((1 << width) - 1)`. Doing the shift first avoids needing a mask positioned at the field's location.

Why do reserved bits matter?

Because most reference manuals require them to keep their reset value, and future silicon may give them meaning. Assigning a whole register clears them; read-modify-write preserves them. Peripherals that behave oddly after a config change are often a symptom of this.

Why does reading a register not return what I wrote?

Several reasons. Write-only bits read as zero. Clear-on-read flags change state when you look at them. Some fields are shadowed and only take effect on an update event. And some are only writable while the peripheral is disabled — the write silently does nothing otherwise.

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