PCB Trace Impedance Calculator — microstrip, stripline, differential

Characteristic impedance for microstrip, stripline and differential pairs — the geometry you need for USB, Ethernet and HDMI.

Example: Microstrip (outer layer) at 0.335 mm wide, 0.2 mm above the plane on εr 4.3: 50 Ω.

Inputs

Topology

Trace width(mm)

Height to plane(mm)

Prepreg or core thickness between the trace and its reference plane.

Copper thickness(mm)

0.035 mm is 1 oz.

Dielectric constant εr

FR4 is 4.2–4.6 and varies with frequency and resin content.

Pair spacing(mm)

Differential only — edge to edge.

Result

Impedance

50 Ω

w/h ratio: 1.675
Effective εr: 3.227
Propagation delay: 0.006 ns/mm
Delay per 100 mm: 0.599 ns

IPC-2141 is a curve fit, good to roughly 5% within its valid range. For a board that must meet a controlled-impedance spec, use the fabricator's stackup and their field solver — they will not guarantee anything computed elsewhere.
Close to the 50 Ω single-ended standard used for most RF and digital signalling.
FR4's εr is not a constant — it falls with frequency and varies with resin content and glass weave, typically 4.2 to 4.6. That spread alone moves impedance by a few percent, which is why tight tolerances need a specified laminate rather than generic FR4.

Impedance against trace width at h = 0.2 mm

Width (mm)	w/h	Impedance
0.1	0.5	85.3 Ω
0.15	0.75	74.4 Ω
0.2	1	66 Ω
0.25	1.25	59.2 Ω
0.335	1.68	50 Ω
0.5	2.5	36.8 Ω
0.75	3.75	23.1 Ω

Formula

microstrip: Z₀ = 87/√(εr+1.41) × ln(5.98h / (0.8w + t))

Calculations follow IPC-2141.

Worked example

Microstrip (outer layer) at 0.335 mm wide, 0.2 mm above the plane on εr 4.3: 50 Ω.

Z₀ = 87/√(εr+1.41) × ln(5.98h / (0.8w + t))
87/√(4.3+1.41) × ln(5.98×0.2 / (0.8×0.335 + 0.035))
49.99 Ω
delay = 3.336 × √εr_eff ps/mm
3.336 × √3.227
6 ps/mm
Length matching uses this — a 10 mm mismatch is about 60 ps on FR4.

Frequently asked questions

What trace width gives 50 ohms?

It depends entirely on the height to the reference plane, not on the width alone. On FR4 with a 0.2 mm prepreg, roughly 0.35 mm. Halve the dielectric height and you halve the width — which is why the stackup matters more than the trace.

Why is differential impedance not just twice the single-ended value?

Because the two traces couple. Fields from one interact with the other, which lowers the differential impedance below 2 × Z₀. Tighter spacing couples more strongly and lowers it further, so spacing is as much a design variable as width.

How accurate are these formulas?

IPC-2141 is a curve fit, good to about 5% within a w/h ratio of 0.1 to 3, and worse outside that. For a controlled-impedance board, use your fabricator's stackup and field solver — they will not guarantee a figure computed anywhere else.

Why does FR4's dielectric constant vary?

FR4 is a family, not a material. Resin content, glass weave style and frequency all move εr, typically between 4.2 and 4.6. That range alone shifts impedance by several percent, which is why tight tolerances require specifying an actual laminate.

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